For high play, the memory does not look at the frequency to see the time. I understand memory timing
DDR5 memory, let more people start paying attention to the frequency of memory products in the frequency, the high-frequency design started from 5000MHz, and it is indeed a lot of users to shock and amazing, and it seems to be a lot of users to buy memory products. Non-two standards. Therefore, it is ignored that in the memory product, an extremely important parameter design, immediate order.
It is also a series of "40-40-40-77", which is marked on major memory products, is highly low. Numerical differences in different products, there will be significant differences, almost a value of a product; in the face of this series of regular values, few people will pay attention to their differences and explore their role, today we will come to a plate Memory timing.
01 What is the timing?
Memory timing, one words refers to a numerical description of the inherent delay encountered during the processing of various task operations, or more essential whitening, the timing is a specific delay in memory processing work and operation. Time, from this definition, the timing is naturally, the better;
At the same time, there is a lot of time series species that affect memory delays, or describe the delay, and four of our regular products are the most affected and most significant part.
They have a specific code. According to the order, TRCD, TRP, TRAS, respectively, the four code all the abbreviation, the first CL, that is, CAS LATENCY, which describes the delay time of the memory column address access, this It is also the most important parameters in timing; second TRCD, Ras To Cas delay, refers to the delay time of the memory address to the column address; the third TRP, ie RAS Precharge Time, indicating that the memory address gate pulse Charging time; the fourth TRAS, RAS Active Time, described in the time of row address activation.
02 How does the timing affect work?
After understanding the main timing meaning, we also need to understand the principles between memory and CPUs to truly understand the impact of the main timing for memory performance.
Typically, the CPU's workflow is to get a addressing instruction, and the memory will quickly search and address files in the cache, and we will address the process of addressed into a row of Go.
When the CPU begins to search the A file, the memory needs to determine which line in the Go lattice, then the second parameter trcd of the timing represents this time, simply, is the instruction of the memory received line, It takes more time to access this line. It is worth noting that because the amount of data in each row is very uncomfortable, it cannot be accurately positioned in the first step in the memory, which can only be an estimate, and thus the second step is required to complete the instruction.
When memory determines which row of A files, it is necessary to confirm which column is to be confirmed. Only when the rows and columns are all determined, they can lock the specific address of the A file; determine the waiting time of the column, it is the timing in the timing, in other words It is the memory to determine the number of rows, how long can it take to access the specific columns.
As for the third parameter, it is to confirm that the first row value is confirmed, and then the time (time period) that needs to wait for another row.
The fourth TRAS section refers to the sum of the entire memory completed commands. Its value is approximately equal to the sum of the top three values. When of course, their difference is huge.
03 Timing comparison of D4 and D5
Below we use DDR4 and DDR5 timing, explore the difference in D4 and D5 memory.
"40-40-40-77" is a 5200MHz D5 product timing design, "16-16-16-36" is the D4 product timing design of this brand.
From the time sequence, there are few more numerical differences in the two, although there is a significant increase in D5 memory on absolute frequencies, which can be severely pulled across the delay, which is undoubtedly an impact on the actual use of the user.
This is why many D5 memory temporarily did not accept a large number of players.
The growth of frequencies does not significantly improve the user experience, and too high latency is like a timed bomb, it will affect the user experience. If you want to have higher frequencies, while reducing the timing, it may be an important topic that has been explored in the future.